1. Technical Field
The present invention generally relates to flat panel display field and, particularly, to a driver integrated circuit (IC) chip and display substrates of flat panel display adapted to electrically couple with a plurality of driver IC chips.
2. Description of the Related Art
Flat panel displays such as a liquid crystal display (LCD) and a plasma display have the advantages of high image quality, small size, light weight and a broad application range, and thus are widely applied on consumer electronic products such as a mobile phone, a notebook computer, a desktop display and a television, and have gradually replaced the traditional cathode ray tube (CRT) displays as the main trend in the display industry.
Referring to FIG. 7, a conventional flat panel display 30 includes a display substrate 31, a printed circuit board 33 and flexible printed circuit boards P1, P2. The flexible printed circuit boards P1, P2 are electrically coupled between the display substrate 31 and the printed circuit board 33.
The display substrate 31 includes a display area 310 (as denoted by the dashed rectangle in FIG. 7), a peripheral area 311 located at sides of the display area 310, a plurality of source driver IC chips SD1˜SD8, a plurality of gate driver IC chips GD1˜GD3 and a plurality of fan-out wiring areas 314. The display area 310 has a plurality of gate control lines GL (of which only one is shown in FIG. 7 for illustration purposes), a plurality of data lines DL (of which only one is shown in FIG. 7 for illustration purposes) and a plurality of display elements P (of which only one is shown in FIG. 7 for illustration purposes) formed therein. The display elements P are electrically coupled to the respective gate control lines GL and the respective data lines DL. The peripheral area 311 has the source driver IC chips SD1˜SD8, the gate driver IC chips GD1˜GD3 and the fan-out wiring areas 314 formed therein. The source driver IC chips SD1˜SD8 contain four groups of cascade connected source driver IC chips respectively coupled to different conductive wires 315 formed on the display substrate 31 by WOA technology. The gate driver IC chips GD1˜GD3 are cascade connected to one conductive wire 315. The fan-out wiring areas 314 are electrically coupled between the respective source driver IC chips SD1˜SD8 and gate driver IC chips GD1˜GD3 and the display area 310.
The printed circuit board 33 generally has a gamma voltage generator and a DC-to-DC converter formed thereon to output a gamma voltage and power signals. The gamma voltage and the power signals then are delivered to the source driver IC chips SD1˜SD8 and the gate driver IC chips GD1˜GD3 through the flexible printed circuit boards P1, P2 and the conductive wires 315. The gamma voltage and the DC-to-DC converter are not drawn in FIG. 7.
The source driver IC chips SD1˜SD8 and the gate driver IC chips GD1˜GD3 are chip-on-glass (COG) chips. FIG. 8 is a schematic enlarged view of any one of the source driver IC chips SD1˜SD8 and the gate driver IC chips GD1˜GD3 being COG chips. Referring to FIGS. 7 and 8, an output side of the COG chip in FIG. 8 has a plurality of output pins 3121, 3131 formed thereat. The output pins 3121 in the dashed frame of FIG. 8 constitute an opened pin group 312 unconnected with any one of the fan-out wiring areas 314. The output pins 3131 constitute a second pin group 313 connected with one of the fan-out wiring areas 314. The opened pin group 312 is located at the middle of the second pin group 313.
FIG. 9 is a schematic enlarged view of any one of the source driver IC chips SD1˜SD8 and the gate driver IC chips GD1˜GD3 being chip-on-film (COF) chips. The COF chip in FIG. 9 includes a flexible film and an IC die mounted on the flexible film. The output pins 3121, 3131 are formed on flexible film. The second pin group 313 on the COF chip is located at two ends of the output side and the opened pin group 312 also is located at the middle of the second pin group 313. It is indicated that, when the source driver IC chips SD1˜SD8 and the gate driver IC chips GD1˜GD3 are COF chips, they are not directly mounted on the display substrate 31 as shown in FIG. 7 but electrically coupled to the display substrate 31 through the respective flexible films of themselves.
However, since the second pin group 313 of each of the driver IC chips SD1˜SD8 and GD1˜GD3 is located at two opposite ends of the output side, which results in transmission paths of the power signals and/or the gamma voltage delivered to the sided output pins 3131 of the second pin groups 313 of the tailmost driver IC chips SD1, SD4, SD5, SD8 and GD3 of the groups of cascade connected driver IC chips are excessive long and thus the power drops are serious. Accordingly, the outputs of the driver IC chips SD1, SD4, SD5, SD8 and GD3 are dramatically influenced by the power drops.